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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
5.9.5
EMIF Electrical Data/Timing CV DD = 1.3 V, DV DDEMIF = 3.3/2.75/2.5/1.8 V, External
Loading = 10 pF
NO.
CV DD = 1.3 V
DV DDEMIF =
3.3/2.75/2.5 V
CV DD = 1.3 V
DV DDEMIF = 1.8 V
UNIT
MIN
MAX
MIN
MAX
19
20
t su(DV-CLKH)
t h(CLKH-DIV)
Input setup time, read data valid on EM_D[15:0] before
EM_SDCLK rising
Input hold time, read data valid on EM_D[15:0] after EM_SDCLK
rising
3.4
1.2
3.4
1.2
ns
ns
(1)
Timing parameters are obtained with 10pF loading on the EMIF pins.
Table 5-17. Switching Characteristics Over Recommended Operating Conditions for EMIF
CV DD = 1.3 V
CV DD = 1.3 V
NO.
PARAMETER
DV DDEMIF = 3.3/2.75/2.5 V
DV DDEMIF = 1.8 V
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
1
2
t c(CLK)
t w(CLK)
Cycle time, EMIF clock EM_SDCLK
Pulse width, EMIF clock EM_SDCLK high or
low
10 (3)
5
20 (4)
10
ns
ns
3
5
7
9
11
13
15
21
t d(CLKH-CSV)
t d(CLKH-DQMV)
t d(CLKH-AV)
t d(CLKH-DV)
t d(CLKH-RASV)
t d(CLKH-CASV)
t d(CLKH-WEV)
t d(CLKH-CKEV)
Delay time, EM_SDCLK rising to
EMA_CS[1:0] valid
Delay time, EM_SDCLK rising to
EM_DQM[1:0] valid
Delay time, EM_SDCLK rising to EM_A[20:0]
and EM_BA[1:0] valid
Delay time, EM_SDCLK rising to EM_D[15:0]
valid
Delay time, EM_SDCLK rising to EM_SDRAS
valid
Delay time, EM_SDCLK rising to EM_SDCAS
valid
Delay time, EM_SDCLK rising to EM_WE
valid
Delay time, EM_SDCLK rising to EM_SDCKE
valid
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
7.77
7.77
7.77
7.77
7.77
7.77
7.77
7.77
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
7.77
7.77
7.77
7.77
7.77
7.77
7.77
7.77
ns
ns
ns
ns
ns
ns
ns
ns
(1)
(2)
(3)
(4)
Timing parameters are obtained with 10pF loading on the EMIF pins.
E = SYSCLK period in ns. For example, when SYSCLK is set to 60 or 100 MHz, E = 16.67 or 10 ns, respectively. For more detail on the
EM_SDCLK speed see Section 5.9.2 , EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported .
When CV DD = 1.3 V, and DV DDEMIF = 3.3 V, 2.75 V or 2.5 V, the max clock frequency on the EM_SDCLK pin is limited to 100 MHz
(EM_SDCLK = 100 MHz). For more information, see TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User's Guide
(literature number SPRUGU6 ).
When DV DDEMIF = 1.8 V, the max clock frequency on the EM_SDCLK pin is limited to 50 MHz (EM_SDCLK = 50 MHz). For more
information, see TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User's Guide (literature number SPRUGU6 ).
96
Peripheral Information and Electrical Specifications
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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